1. Field of the Invention
The present invention relates to concurrency mechanisms and, in particular, to instruction set processors, methods and program products that implement or exploit conditional multi-store synchronization.
2. Description of the Related Art
Synchronization techniques based on use of load-linked/store-conditional (LL/SC) instruction pairs have been supported in a variety of processor designs, including at least some processors based on MIPS, Alpha, and PowerPC instruction set architectures. Unfortunately, current implementations of LL/SC synchronization techniques present limitations that affect their usefulness for coordination of competing computations. For example, only a single store can be made conditional upon a previous load. Also, implementations typically require that a store-conditional instruction target the same memory location as the preceding load-linked.
Transactional memory provides another framework for coordination amongst competing computations. Indeed, a variety of designs for transactional memory and similar mechanisms appear in the literature. Unfortunately, the strong semantics of transactional memory mechanisms (at least as typically proposed) tends to result in complex implementation requirements and, as a practical matter, imposes limits on scaling of transaction read and/or write sets. In general, a transactional memory monitors locations read previously and prevents subsequent stores from taking effect if a monitored location changes. However, transactional memory and related mechanisms must buffer all stores, ensuring that none of them takes effect, until the entire sequence (or transaction) is completed. This naturally imposes limits on the number of stores that can be executed by any transaction. Furthermore, transactional memory may have to monitor multiple locations that are read by the transaction. This again imposes limitations. For example, in a design based on monitoring cache lines in a 4-way set associative cache, a particular transaction might happen to access 5 variables that all map to the same cache set, and such a transaction is doomed to fail deterministically.
In general, it would be desirable if programmers did not have to reason about such things. Alternative techniques are desired.